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(parent: f3bbcc7) | patch
x86: Intel EPT entry structure changes.
authorKeir Fraser <keir.fraser@citrix.com>
Thu, 4 Feb 2010 09:04:33 +0000 (09:04 +0000)
committerKeir Fraser <keir.fraser@citrix.com>
Thu, 4 Feb 2010 09:04:33 +0000 (09:04 +0000)
commit22cce0547c784c101b60e06c6cabc9c1b64aac82
tree85ab808bdb103b958c49854568b36a8f05e32b1ctree | snapshot
parentf3bbcc79956e7b6d38587c4de0dd1feb24b5f358commit | diff
x86: Intel EPT entry structure changes.

 - Intel SDM defines bit6 in EPT page table entry as "Ignore PAT
   memory type", so change the abbreviation from "igmt" to "ipat".

 - Change the mfn and avail2 fields according to SDM definition.

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
xen/arch/x86/hvm/mtrr.c diff | blob | history
xen/arch/x86/mm/hap/p2m-ept.c diff | blob | history
xen/include/asm-x86/hvm/vmx/vmx.h diff | blob | history
xen/include/asm-x86/mtrr.h diff | blob | history
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